Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Exact calculation of synchronization sequences based on binary decision diagrams
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On computing the transitive closure of a state transition relation
DAC '93 Proceedings of the 30th international Design Automation Conference
Verus: a tool for quantitative analysis of finite-state real-time systems
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Improved reachability analysis of large finite state machines
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of systems containing counters
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computing timed transition relations for sequential cycle-based simulation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Abstraction from counters: an application on real-time systems
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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Symbolic Techniques have undergone major improvements but extending their applicability to new fields is still a key issue. A great limitation on standard Symbolic Traversals is represented by Finite State Machines with a very high sequential depth. A typical example of this behaviour are counters. On the other hand systems containing counters, e.g. embedded systems, are of great practical importance in several fields. Iterative squaring can produce solutions with a logarithmic execution time with respect to the sequential depth but a few drawbacks usually limit its application. We successfully tailored iterative squaring to allow its application for symbolic verification and synthesis of circuits containing counters. Experiments on large and complex home-made and industrials circuits containing counters show the feasibility of the approach.