The Unified Modeling Language user guide
The Unified Modeling Language user guide
Software reliability methods
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
Formal Verification of UML Statecharts with Real-Time Extensions
FASE '02 Proceedings of the 5th International Conference on Fundamental Approaches to Software Engineering
Model Checking of Message Sequence Charts
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Extension of UML Sequence Diagrams for Real-Time Systems
«UML» '98 Selected papers from the First International Workshop on The Unified Modeling Language «UML»'98: Beyond the Notation
Scenario-Based Specifications Verification for Component-Based Embedded Software Designs
ICPPW '05 Proceedings of the 2005 International Conference on Parallel Processing Workshops
Timed sequence diagrams and tool-based analysis: a case study
UML'99 Proceedings of the 2nd international conference on The unified modeling language: beyond the standard
Modelling and analysis of power consumption for component-based embedded software
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
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In this paper, for real-time embedded software we consider the problem of checking component-based designs for scenario-based timing specifications. By adding time intervals on the actions, we extend the interface automata for modelling real-time systems. The component-based designs are modelled by real-time interface automaton networks, which includes a set of real-time interface automata synchronized by shared actions, and the scenario-based timing specifications are specified by UML sequence diagrams with a set of boolean expressions. Based on analyzing the compatible integer state space of a real-time interface automaton network and its compatible reachability graph, we develop an algorithm to check the consistency between real-time component-based designs and the scenario-based timing specifications.