Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
A Tutorial on Stålmarck‘s Proof Procedure for PropositionalLogic
Formal Methods in System Design - Special issue on formal methods for computer-added design
Introducing Core-Based System Design
IEEE Design & Test
PVS: Combining Specification, Proof Checking, and Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
The Semantic Challenge of Verilog HDL
LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science
Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving
Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving
An Introduction to Formal Hardware Verification
An Introduction to Formal Hardware Verification
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
The Design and Verification of a Sorter Core
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic analysis of DMA races using model checking and k-induction
Formal Methods in System Design
Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Tightening test coverage metrics: a case study in equivalence checking using k-induction
FMCO'10 Proceedings of the 9th international conference on Formal Methods for Components and Objects
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A formal verification technique is presented which is suitable for the verification of standard components (cores) for programmable hardware (FPGAs). This technique can be viewed as a suitable complement to traditional techniques, such as simulation. We describe the modelling and verification of combinational and sequential components using the formal verification tool NP-Tools, and report successful verification of real cores.