Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Formal hardware verification by integrating HOL and MDG
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Formal verification of the FPGA cores
Nordic Journal of Computing
ACM SIGDA Newsletter
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
Hi-index | 0.01 |
Formal hardware verification has recently attracted considerable interest. The need for ``correct'''' designs in safety-critical applications, coupled with the major cost associated with products delivered late, are two of the main factors behind this. In addition, as the complexity of the designs increase, an ever smaller percentage of the possible behaviors of the designs will be simulated. Hence, the confidence in the designs obtained by simulation is rapidly diminishing. This paper provides an introduction to the topic by describing three of the main approaches to formal hardware verification: theorem-proving, model checking and symbolic simulation. We outline the underlying theory behind each approach, we illustrate the approaches by applying them to simple examples and we discuss their strengths and weaknesses. We conclude the paper by describing current on-going work on combining the approaches to achieve multi-level verification approaches.