The periodic balanced sorting network
Journal of the ACM (JACM)
Formal verification of the FPGA cores
Nordic Journal of Computing
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Functional Design Using Behavioural and Structural Components
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Functional and dynamic programming in the design of parallel prefix networks
Journal of Functional Programming
Obsidian: a domain specific embedded language for parallel programming of graphics processors
IFL'08 Proceedings of the 20th international conference on Implementation and application of functional languages
Expressive array constructs in an embedded GPU kernel programming language
DAMP '12 Proceedings of the 7th workshop on Declarative aspects and applications of multicore programming
Wired: wire-aware circuit design
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Formal verification of hardware synthesis
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We show how the Lava system is used to design and analyse fast sorting circuits for implementation on Field Programmable Gate Arrays (FPGAs). We present both recursive and periodic sorting networks, based on recursive merging networks such as Batcher's bitonic and odd-even mergers. We show how a design style that concentrates on capturing connection patterns gives elegant generic circuit descriptions. This style aids circuit analysis and also gives the user fine control of the final layout on the FPGA. We demonstrate this by analysing and implementing four sorters on a Xilinx Virtex-II™ FPGA. Performance figures are presented.