Sorting networks and their applications

  • Authors:
  • K. E. Batcher

  • Affiliations:
  • Goodyear Aerospace Corporation, Akron, Ohio

  • Venue:
  • AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
  • Year:
  • 1968

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Abstract

To achieve high throughput rates today's computers perform several operations simultaneously. Not only are I/O operations performed concurrently with computing, but also, in multiprocessors, several computing operations are done concurrently. A major problem in the design of such a computing system is the connecting together of the various parts of the system (the I/O devices, memories, processing units, etc.) in such a way that all the required data transfers can be accommodated. One common scheme is a high-speed bus which is time-shared by the various parts; speed of available hardware limits this scheme. Another scheme is a cross-bar switch or matrix; limiting factors here are the amount of hardware (an m × n matrix requires m × n cross-points) and the fan-in and fan-out of the hardware.