Storage coding for wear leveling in flash memories

Authors:
Anxiao Jiang;Robert Mateescu;Eitan Yaakobi;Jehoshua Bruck;Paul H. Siegel;Alexander Vardy;Jack K. Wolf
Affiliations:
Department of Computer Science, Texas A&M University, College Station, TX;California Institute of Technology, Pasadena, CA;Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA;California Institute of Technology, Pasadena, CA;Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA;Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA;Electrical and Computer Engineering, University of California, San Diego, La Jolla, CA
Venue:
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 2
Year:
2009

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Abstract

NAND flash memories are currently the most widely used flash memories. In a NAND flash memory, although a cell block consists of many pages, to rewrite one page, the whole block needs to be erased and reprogrammed. Block erasures determine the longevity and efficiency of flash memories. So when data is frequently reorganized, which can be characterized as a data movement process, how to minimize block erasures becomes an important challenge. In this paper, we show that coding can significantly reduce block erasures for data movement, and present several optimal or nearly optimal algorithms. While the sorting-based non-coding schemes require O(n log n) erasures to move data among n blocks, coding-based schemes use only O(n) erasures and also optimize the utilization of storage space.