The complexity of Boolean functions
The complexity of Boolean functions
Lower bounds for sorting networks
STOC '95 Proceedings of the twenty-seventh annual ACM symposium on Theory of computing
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Balancing networks: state of the art
Information Sciences: an International Journal - Special issue: load balancing in distributed systems
Improved routing and sorting on multibutterflies
STOC '97 Proceedings of the twenty-ninth annual ACM symposium on Theory of computing
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Efficient VLSI architectures for Columnsort
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
How to Sort N Items Using a Sorting Network of Fixed I/O Size
IEEE Transactions on Parallel and Distributed Systems
A self-timed real-time sorting network
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Minimizing Communication in the Bitonic Sort
IEEE Transactions on Parallel and Distributed Systems
Parallel Sorting Algorithms
Information Sciences—Applications: An International Journal
Tight bounds on the complexity of parallel sorting
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
GPUTeraSort: high performance graphics co-processor sorting for large database management
Proceedings of the 2006 ACM SIGMOD international conference on Management of data
A scalable VLSI speed/area tunable sorting network
Journal of Systems Architecture: the EUROMICRO Journal
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Accelerating certain outputs of merging and sorting networks
Theoretical Computer Science
Efficient unbalanced merge-sort
Information Sciences: an International Journal
Optimal conclusive sets for comparator networks
SIROCCO'07 Proceedings of the 14th international conference on Structural information and communication complexity
The Strongest Model of Computation Obeying 0-1 Principles
Theory of Computing Systems
TELE-INFO'11/MINO'11/SIP'11 Proceedings of the 10th WSEAS international conference on Telecommunications and informatics and microelectronics, nanoelectronics, optoelectronics, and WSEAS international conference on Signal processing
Hi-index | 0.07 |
This paper extends previous work on sorting networks (SNs) based on min/max circuits. In particular, we have identified the complexity of both min/max-based sorting and merging networks showing that, depending on design choice, the time complexity of this kind of SN ranges from O(1) to O(log (n)) and spatial complexity from O(n2^n) to O(n^2), respectively. Moreover, we show that both AT and AT^2 metrics of the proposed SN are better than those of Batcher's SNs also for SNs with several hundreds of inputs. In addition to these results we show how to design a fast digital, serial, pipelined sorting network using FPGA technology. As expected, FPGA synthesis results confirm our theoretical analysis.