A scalable VLSI speed/area tunable sorting network

Authors:
Giuseppe Campobello;Marco Russo
Affiliations:
Faculty of Engineering, University of Messina, Contrada di Dio, Messina, Italy;Department of Physics and Astronomy, University of Catania and National Institute of Nuclear Physics (INFN) Section of Catania, Catania, Italy
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2006

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Abstract

This work presents a novel sorting network based on the "sorting by counting" algorithm. The proposed implementation of the algorithm is very regular. Further, its realization depends on a design parameter, that permits different tradeoffs between speed and area to be chosen. For example, we can fix this parameter to obtain a feasible SN with n inputs and O(log(n)) elaboration time with a reasonable multiplicative constant. Comparisons with previous works show that under some metrics for a wide range of values of n we obtain the best results.