A Non-binary Parallel Arithmetic Architecture
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
IEEE Transactions on Parallel and Distributed Systems
A scalable VLSI speed/area tunable sorting network
Journal of Systems Architecture: the EUROMICRO Journal
Improving the average delay of sorting
Theoretical Computer Science
Improving the average delay of sorting
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
On the complexity of min-max sorting networks
Information Sciences: an International Journal
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This paper presents novel very large scale integration (VLSI) architectures in support of an efficient implementation of Leighton's well-known Columnsort. The designs take advantage of reconfigurable bus architectures enhanced with simple shift switches. Our first main contribution is to show that Columnsort can be partitioned into two components: a hardware scheme involving the task of sorting arrays of small size and a hardware or software scheme that involves simple data movement tasks. Our second main contribution is to demonstrate that the dynamically reconfigurable mesh architecture can be exploited to obtain a small and efficent hardware sorter. The resulting architectures feature high regularity of circuitry, simplicity of control structure, and adaptability. Both theoretical analyses and simulation tests have shown that the proposed VLSI architectures for sorting are superior to existing designs in the context of sorting small and moderate size arrays.