Parallel Computations on Reconfigurable Meshes
IEEE Transactions on Computers
Reconfigurable Buses with Shift Switching: Concepts and Applications
IEEE Transactions on Parallel and Distributed Systems
Efficient VLSI architectures for Columnsort
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable Hardware-Algorithms for Binary Prefix Sums
Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
Shift switching and novel arithmetic schemes
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.