Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh
IEEE Transactions on Parallel and Distributed Systems
A Non-binary Parallel Arithmetic Architecture
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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High speed shift switching with CMOS and precharged CMOS techniques are proposed for arithmetic designs with existing technology, which can substantially increase speed and/or reduce area for parallel counters. The transmission-gate-based shift switches are cascaded to synthesize an N-bit parallel counter, achieving a delay of (log(N+1)-1) times a full adder delay. The pass-transistor-based shift switches are cascaded to construct fast domino chains, which differ from the traditional (precharged CMOS NP) domino chains (on data paths) mainly in that they can readily provide a semaphore to indicate the end of the domino process. This suggests a new approach for asynchronous arithmetic.