Tight bounds on the complexity of parallel sorting
IEEE Transactions on Computers
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Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.)
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Communications of the ACM
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IEEE Transactions on Parallel and Distributed Systems
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
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ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
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Information Sciences: an International Journal
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Journal of Parallel and Distributed Computing
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This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an $\Omega$-network of $(\log N- 1)$ switch levels. This network reduces the cost complexity to $O(N \log N)$ compared with the $O(N \log^{2} N)$ of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network.