Minimizing Communication in the Bitonic Sort
IEEE Transactions on Parallel and Distributed Systems
Parallel Sorting Algorithms
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Efficient Massively Parallel Quicksort
IRREGULAR '97 Proceedings of the 4th International Symposium on Solving Irregularly Structured Problems in Parallel
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Bitonic Sort on a Mesh-Connected Parallel Computer
IEEE Transactions on Computers
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Computers and Electrical Engineering
Bitonic sort on a chained-cubic tree interconnection network
Journal of Parallel and Distributed Computing
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This paper presents a bitonic sort scheme in a shared memory mesh-connected SIMD array processor. In addition, it uses the two types of comparators of sorting networks in the mesh-connected parallel computer. This scheme uses variable multiple pivots and non-pivots. Parity strategy has been implemented to minimize the number of accesses in the mesh-connected interconnection network by introducing the concept of global and local memory. The proposed scheme is sufficiently general which is independent of hardware and interconnection network among them. From results it has been observed that by reducing the internetwork communication a performance improvement is achieved.