A self-timed real-time sorting network

  • Authors:

  • Kenneth Y. Yun;Kevin W. James;Rene L. Cruz;Robert H. Fairlie-Cuninghame;Supratik Chakraborty

  • Affiliations:

  • Univ. of California at San Diego, La Jolla;Univ. of California at San Diego, La Jolla;Univ. of California at San Diego, La Jolla;Nuera Communications, San Diego, CA;Fujitsu Labs of America, Sunnyvale, CA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
  • Year:
  • 2000

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Abstract

High-speed networks are expected to carry traffic classes with diverse quality of service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however, these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet switches that support a diverse mix of traffic. The sorting network receives packets with appropriately assigned priorities and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, and self-precharging domino logic to minimize the circuit latency. An experimental sorting network chip has been designed using the techniques described in this paper to support 10 Gb/s links with ATM-size packets.