An FPGA Architecture for High Speed Edge and Corner Detection
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Performance of reconfigurable architectures for image-processing applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Image Processing Algorithms on Reconfigurable Architecture using HandelC
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
A Generalized Bitonic Sorting Network
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
A reconfigurable computing framework for multi-scale cellular image processing
Microprocessors & Microsystems
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Designing mathematical morphology algorithms on FPGAs: an application to image processing
CAIP'05 Proceedings of the 11th international conference on Computer Analysis of Images and Patterns
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology
Objects detection and tracking in highly congested traffic using compressed video sequences
ICCVG'12 Proceedings of the 2012 international conference on Computer Vision and Graphics
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Feature extraction is an important stage in image processing for object classification, tracking or identification. Real time processing adds stringent constraints on the efficiency of this task. The paper presents a discussion of a reconfigurable hardware processing architecture, based on components, for performing feature calculations using convolutions, morphology operators and local statistics. Special attention is directed to pipelining calculations, fast determination of minimum, median and maximum of values. The architecture is optimised for video streams, which provide the image contents using horizontal scanning. An implementation using a low cost FPGA is presented proving the feasibility of this approach.