Digital image processing (2nd ed.)
Digital image processing (2nd ed.)
Introduction to parallel digital image processing
Parallel algorithms
Spyder: a SURE (SUperscalar and REconfigurable) processor
The Journal of Supercomputing - Special issue on field programmable gate arrays
Journal of Systems Architecture: the EUROMICRO Journal
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Performance of image and video processing with general-purpose processors and media ISA extensions
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Computers
PipeRench implementation of the instruction path coprocessor
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Cache performance for multimedia applications
ICS '01 Proceedings of the 15th international conference on Supercomputing
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
The Garp Architecture and C Compiler
Computer
Challenges and Opportunities for FPGA Platforms
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An Evaluation of an FPGA Run-Time Support System
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Header Compression in Handel-C -- An Internet Application and a New Design Language
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Reconfigurable Computing: A New Business Model and its Impact on SoC Design
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Augmenting a microprocessor with reconfigurable hardware
Augmenting a microprocessor with reconfigurable hardware
Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Feature extraction using reconfigurable hardware
ICCVG'10 Proceedings of the 2010 international conference on Computer vision and graphics: Part II
Performance and power evaluation of an intelligently adaptive data cache
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Journal of Systems Architecture: the EUROMICRO Journal
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Reconfigurable architectures combine a programmable-visible interface and the high-level aspects of a computer's design. The goal of this work is to explore the architectural behaviour of remote reconfigurable systems that are part of general-purpose computers. Our approach analyses various issues arising from the connection of processors with FPGA-based microarchitecture to an existing commodity microprocessor via a standard bus. The quantitative evaluation considers image-processing applications and shows that the maximum performance depends on the amount of data processed by the reconfigurable hardware. Taking images with 256 × 256 pixels, a moderate FPGA capacity of 1E+5 logic blocks provides two orders of magnitude of performance improvement over a Pentium III processor for most of our benchmarks. However, the performance benefits exhibited by reconfigurable architectures may be deeply influenced by some design parameters. This paper studies the impact of hardware capacity, reconfiguration time, memory organisation, and bus bandwidth on the performance achieved by FPGA-based systems. Those image-processing benchmarks that can exhibit high-performance improvement would require about 150 memory banks of 256 bytes each and a bus bandwidth as high as 30 GB/s. This quantitative approach can be applied to the design of high-performance reconfigurable coprocessors for multimedia applications.