A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model

Authors:
Kazuya Tanigawa;Tetsuo Hironaka;Akira Kojima;Noriyoshi Yoshida
Affiliations:
-;-;-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

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Abstract

In this paper, we consider the possibility of using a reconfigurable architecture as a general-purpose computer. Many reconfigurable architectures have been proposed. However, these architectures are hard to use as a general-purpose computer because their architectures have no explicit execution model for software developments. Therefore, in this paper, we propose an Ideal PARallel Structure (I-PARS) execution model. To make software developments easily, the program based on the I-PARS execution model has no limitation depending on the hardware structure of the processor based on any reconfigurable architectures. Also, we propose a PARS architecture to execute programs based on the I-PARS execution model effectively. Further, we implement a prototype processor based on the PARS architecture and estimated its performance. From the implementation and the estimation, we show the feasibility of programming on the I-PARS execution model and executing it on the PARS architecture.