VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
A back-end compiler with fast compilation for VLIW based dynamic reconfigurable processor
WSEAS Transactions on Computers
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We have proposed and developed a compiler for dynamic reconfigurable processor based on VLIW model. VLIW model, which is our compiler targets, fetches and executes one configuration data as VLIW instruction. For this model, our compiler schedules mapping elements as operations and live variables in program, with consideration of hardware resources. Next, it places and routes the elements to hardware resources. In place-and-route, if the number of mapping elements in one configuration data is large, place-and-route condition is so difficult that the number of final steps might be worse. The number of mapping elements is significant important, because output result is widely different by depending on the number of mapping elements, and the optimal number of them is also different depending on the nature of applications. To search the optimal number of them and improve scheduling and place-and-route results, we propose a novel mapping method which dynamically changes the maximum number of mapping elements as parameters. To solve the previous problem, we adopt heuristic approach. As one of target processors based on VLIW model, we use PARS processor which dynamically reconfigurates and executes one configuration data as one VLIW instruction every cycle. We evaluate our method by the number of generated configuration data. And the comparative method is ones which uses constant parameters which is statically set by depending on the hardware resources of target processor. From the results, our method can find more optimal parameters for each application, and decrease 22.6% of the number of configuration data in maximum (13.4% in average), compared with the comparative method.