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We have developed a compiler for dynamic reconfigurable processor based on VLIW model. VLIW model fetches and executes one configuration data as VLIW instruction. For this model, our compiler schedules mapping elements as operations and live variables in program, with consideration of hardware resources. Next, place-and-route procedure places and routes the mapping elements to hardware resources for several configuration data. However the conventional place-and-route algorithms require much compilation time. The reason is that, for difficulty place-and-route condition, the number of place-and-route iteration is increased to get high code quality. Thus we propose a novel compiler method, which is combining scheduling and place-and-route with fast compilation, on keeping code quality. Our idea is that if a scheduling simplifies the place-and-route condition, small compilation time of place-and-route can realize a reasonable code quality. In scheduling, to balance the number of operations and live variables, and make the place-and-route condition easy, the operations are moved to another step with a fewer operations. In place-and-route, to reduce iteration procedures to get the reasonable result, it limits targets for replace-and-reroute. In this paper, we use PARS as one of target processors based on VLIW model. We evaluate our method and compare it with another method based on Simulated Annealing (SA). From the results, our method achieves that the difference of code quality (the number of configuration data like VLIW instruction) is -3.4% - +1.2%, and compilation time is cut to 1/128 - 1/67, compared with SA base method.