Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Design Technology for Networked Reconfigurable FPGA Platforms
Proceedings of the conference on Design, automation and test in Europe
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
Performance of reconfigurable architectures for image-processing applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
Proceedings of the conference on Design, automation and test in Europe
The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
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Today, FPGA devices contain up to 10 million system gates [1] and within three to four years processing technology will allow us to build 50 million gate devices, i.e. enough logic to build very complex, high performance systems. In addition, these devices operate at internal clock speeds, the equal of most ASIC's. Although the opportunities for building complex systems with these FPGA platforms are unprecedented, new breakthroughs will be required to solve