VLSI architectures for turbo codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
Dynamic Reconfiguration in Mobile Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Challenges and Opportunities for FPGA Platforms
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Mapping wireless communication algorithms onto a reconfigurable architecture
The Journal of Supercomputing
Towards software defined radios using coarse-grained reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A framework for low energy data management in reconfigurable multi-context architectures
Journal of Systems Architecture: the EUROMICRO Journal
Computers and Electrical Engineering
An efficient placement algorithm for run-time reconfigurable embedded system
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Non-power-of-two FFTs: exploring the flexibility of the montium TP
International Journal of Reconfigurable Computing
Domain specific architecture for next generation wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A pattern selection algorithm for multi-pattern scheduling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient resource sharing architecture for multistandard communication system
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Context-adaptive and energy-efficient mobile transaction management in pervasive environments
The Journal of Supercomputing
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
Partial online-synthesis for mixed-grained reconfigurable architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Two of the most important design issues for next generation handheld devices are wireless networking and the processing of multimedia content. Both applications rely heavily on computationally intensive digital signal processing algorithms. Programmable architectures that keep pace with the increasing performance requirements become more and more power hungry. This is problematic for a battery powered mobile device, since it has only a limited amount of energy available. Conversely, dedicated architectures are too inflexible to keep pace with changing standards and feature sets. A mobile device requires high-performance, flexibility and (energy-)efficiency. These contradicting requirements need to be balanced in the system architecture of a mobile device. In this paper a heterogeneous architecture of domain specific processing tiles is proposed. The focal point is the coarse-grained reconfigurable architecture of the Montium processing tile, which is designed to execute digital signal processing algorithms energy-efficiently.