Mapping of DSP Algorithms on the MONTIUM Architecture
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
A high-speed CMOS implementation of the Winograd Fourier transformalgorithm
IEEE Transactions on Signal Processing
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Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation.