The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
A medium-grain reconfigurable architecture for DSP: VLSI design, benchmark mapping, and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-power-of-two FFTs: exploring the flexibility of the montium TP
International Journal of Reconfigurable Computing
Microprocessors & Microsystems
Systolic algorithm mapping for coarse grained reconfigurable array architectures
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Full length article: Cognitive Radio baseband processing on a reconfigurable platform
Physical Communication
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In battery operated mobile devices there is a growing need for flexible high-performance architectures due to the limited amount of available energy and the increasing demand of processing power. Course grained reconfigurable architectures could be the key to more energy-efficient, yet programmable systems. In this paper a course-grained reconfigurablearchitecture, called MONTIUM, is presented. Several mappings of commonly used digital signal processing algorithms are shown to demonstrate the flexibility of this architecture.