Evaluation of a reconfigurable architecture for digital beamforming using the OODRA workbench
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A Reconfigurable Computing Architecture for Microsensors
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Mapping of DSP Algorithms on the MONTIUM Architecture
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Massively Parallel Wireless Reconfigurable Processor Architecture and Programming
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
The Chameleon architecture for streaming DSP applications
EURASIP Journal on Embedded Systems
Multi-core architectures and streaming applications
Proceedings of the 2008 international workshop on System level interconnect prediction
Towards software defined radios using coarse-grained reconfigurable hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The CORDIC computing technique
IRE-AIEE-ACM '59 (Western) Papers presented at the the March 3-5, 1959, western joint computer conference
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
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Traditionally, mechanically steered dishes or analog phased array beamforming systems have been used for radio frequency receivers, where strong directivity and high performance were much more important than low-cost requirements. Real-time controlled digital phased array beamforming could not be realized due to the high computational requirements and the implementation costs. Today, digital hardware has become powerful enough to perform the massive number of operations required for real-time digital beamforming. With the continuously decreasing price per transistor, high performance signal processing has become available by using multi-processor architectures. More and more applications are using beamforming to improve the spatial utilization of communication channels, resulting in many dedicated digital architectures for specific applications. By using a reconfigurable architecture, a single hardware platform can be used for different applications with different processing needs. In this article, we show how a reconfigurable multi-processor system-on-chip based architecture can be used for phased array processing, including an advanced tracking mechanism to continuously receive signals with a mobile satellite receiver. An adaptive beamformer for DVB-S satellite reception is presented that uses an Extended Constant Modulus Algorithm to track satellites. The receiver consists of 8 antennas and is mapped on three reconfigurable Montium TP processors. With a scenario based on a phased array antenna mounted on the roof of a car, we show that the adaptive steering algorithm is robust in dynamic scenarios and correctly demodulates the received signal.