Systolic algorithm mapping for coarse grained reconfigurable array architectures

Authors:
Kunjan Patel;C. J. Bleakley
Affiliations:
UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and Informatics, University College Dublin, Dublin 4, Ireland;UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and Informatics, University College Dublin, Dublin 4, Ireland
Venue:
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Year:
2010

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Abstract

Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on the same architecture. This paper investigates systolic mapping techniques for mapping biosignal processing algorithms to CGRA architectures. A novel methodology using synchronous data flow (SDF) graphs and control and data flow (CDF) graphs for mapping is presented. Mapping signal processing algorithms in this manner is shown to give up to a 88% reduction in memory accesses and significant savings in fetch and decode operations while providing high throughput.