The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Multiple-banked register file architectures
Proceedings of the 27th annual international symposium on Computer architecture
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Reducing register ports for higher speed and lower energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Mapping of DSP Algorithms on the MONTIUM Architecture
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Deterministic parallel processing
International Journal of Parallel Programming
Fundamentals of WiMAX: Understanding Broadband Wireless Networking (Prentice Hall Communications Engineering and Emerging Technologies Series)
An ILP formulation for system-level application mapping on network processor architectures
Proceedings of the conference on Design, automation and test in Europe
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The reconfigurable instruction cell array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
An ILP formulation for task mapping and scheduling on multi-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Software implementation of WiMAX on the sandbridge sandblaster platform
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Hi-index | 0.03 |
Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such as speed, power, and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an application-specific integrated circuit, emerging dynamically reconfigurable (DR) processors are proving to be strong candidates for processing cores in future high-performance multicore-processor systems. This paper presents several new single-chip multicore architectures for the WiMAX application based on recently emerging coarse-grained DR processor cores. A simulation platform is proposed in order to explore and implement various multicore solutions combining different memory architectures and task-partitioning schemes. This paper describes the different architectures, the simulation environment, and several task-partitioning methods and demonstrates that up to 7.3 and 12 times speedup can be achieved by employing eight and ten DR processor cores for both the WiMAX transmitter and receiver sections, respectively. A comparison with other WiMAX multicore solutions is given in order to demonstrate that our best solution delivers a high throughput at relatively low area cost.