Automated dynamic throughput-constrained structural-level pipelining in streaming applications
Proceedings of the conference on Design, automation and test in Europe
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Diastolic arrays: throughput-driven reconfigurable computing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RETHROTTLE: execution throttling in the REDEFINE SoC architecture
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Proceedings of the 9th conference on Computing Frontiers
Occam-pi for programming of massively parallel reconfigurable architectures
International Journal of Reconfigurable Computing
Silicon-aware distributed switch architecture for on-chip networks
Journal of Systems Architecture: the EUROMICRO Journal
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A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using software languages and methodologies. Its objectives are massive performance, long-term scalability, and easy development. In our structural object programming model, objects are strictly encapsulated software programs running concurrently on an asynchronous array of processors and memories. They exchange data and control through a structure of self-synchronizing asynchronous channels. Objects are combined hierarchically to create new objects, connected through the common channel interface. The first chip is a 130nm ASIC with 360 32-bit processors, 360 1KB RAM banks with access engines, and a configurable word-wide channel interconnect. Applications written in Java and block diagrams compile in one minute. Sub-millisecond runtime reconfiguration is inherent.