Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
A three dimensional register file for superscalar processors
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Optimization of high-performance superscalar architectures for energy efficiency
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Exploiting data forwarding to reduce the power budget of VLIW embedded processors
Proceedings of the conference on Design, automation and test in Europe
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
Run-time power estimation in high performance microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Quantifying and enhancing power awareness of VLSI systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Design and Realization of a Low Power Register File Using Energy Model
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Inter-Cluster Communication Models for Clustered VLIW Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Banked multiported register files for high-frequency superscalar microprocessors
Proceedings of the 30th annual international symposium on Computer architecture
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files
Proceedings of the 2003 international symposium on Low power electronics and design
A Content Aware Integer Register File Organization
Proceedings of the 31st annual international symposium on Computer architecture
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Speculative Control Scheme for an Energy-Efficient Banked Register File
IEEE Transactions on Computers
An asymmetric clustered processor based on value content
Proceedings of the 19th annual international conference on Supercomputing
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining
IEEE Transactions on Computers
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Bypass aware instruction scheduling for register file power reduction
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
A case for a complexity-effective, width-partitioned microarchitecture
ACM Transactions on Architecture and Code Optimization (TACO)
Register port complexity reduction in wide-issue processors with selective instruction execution
Microprocessors & Microsystems
Integration, the VLSI Journal
Achieving Out-of-Order Performance with Almost In-Order Complexity
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Energy-aware register file re-partitioning for clustered VLIW architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupled state-execute architecture
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
CRAM: coded registers for amplified multiporting
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
An optimized front-end physical register file with banking and writeback filtering
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Compiler-driven leakage energy reduction in banked register files
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Scheduling for register file energy minimization in explicit datapath architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Shared-port register file architecture for low-energy VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
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Register files (RF) represent a substantial portion of the energybudget in modern processors, and are growing rapidly with the trendtowards wider instruction issue. The actual access energy costsdepend greatly on the register file circuitry used. This papercompares various RF circuitry techniques for their energy ef-ficiencies, as a function of architectural parameters such as thenumber of registers and the number of ports. The Port PrioritySelection technique was found to be the most energy efficient. Thedependence of register file access energy upon technology scalingis also studied. However, as this paper shows, it appears that noneof these will be enough to prevent centralized register files frombecoming the dominant power component of next-generationsuperscalar computers, and alternative methods forinter-instruction communication need to be developed. Splitregister file architecture is analyzed as a possible alternative.