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Complexity-effective superscalar processors
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The energy complexity of register files
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MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
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Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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Future Generation Computer Systems
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There is still much performance to be gained by out-of-order processors with wider issue widths. However, traditional methods of increasing issue width do not scale; that is, they drastically increase design complexity and power requirements. This paper introduces the braid, a compile-time identified entity that enables the execution core to scale to wider widths by exploiting the small fanout and short lifetime of values produced by the program. Braid processing requires identification by the compiler, minor extensions to the ISA, and support by the microarchitecture. The result from processing braids is performance within 9% of a very aggressive conventional out-of-order microarchitecture with almost the complexity of an in-order implementation.