Trace processors

  • Authors:

  • Eric Rotenberg;Quinn Jacobson;Yiannakis Sazeides;Jim Smith

  • Affiliations:

  • Computer Sciences Dept., and Dept. of Electrical and Computer Engineering, University of Wisconsin - Madison;Computer Sciences Dept., University of Wisconsin - Madison;Computer Sciences Dept., University of Wisconsin - Madison;Computer Sciences Dept., University of Wisconsin - Madison

  • Venue:
  • MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1997

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Abstract

Traces are dynamic instruction sequences constructed and cached by hardware. A microarchitecture organized around traces is presented as a means for efficiently executing many instructions per cycle. Trace processors exploit both control flow and data flow hierarchy to overcome complexity and architectural limitations of conventional superscalar processors by (1) distributing execution resources based on trace boundaries and (2) applying control and data prediction at the trace level rather than individual branches or instructions. Three sets of experiments using the SPECInt95 benchmarks are presented. (i) A detailed evaluation of trace processor configurations: the results affirm that significant instruction-level parallelism can be exploited in integer programs (2 to 6 instructions per cycle). We also isolate the impact of distributed resources, and quantify the value of successively doubling the number of distributed elements. (ii) A trace processor with data prediction applied to inter-trace dependences: potential performance improvement with perfect prediction is around 45% for all benchmarks. With realistic prediction, gcc achieves an actual improvement of 10%. (iii) Evaluation of aggressive control flow: some benchmarks benefit from control independence by as much as 10%.