Scalable selective re-execution for EDGE architectures

  • Authors:

  • Rajagopalan Desikan;Simha Sethumadhavan;Doug Burger;Stephen W. Keckler

  • Affiliations:

  • The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin;The University of Texas at Austin

  • Venue:
  • ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
  • Year:
  • 2004

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Abstract

Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affected by the mis-speculation, instead of all instructions. In this paper we introduce a new selective re-execution mechanism that exploits the properties of a dataflow-like Explicit Data Graph Execution (EDGE) architecture to support efficient mis-speculation recovery, while scaling to window sizes of thousands of instructions with high performance. This distributed selective re-execution (DSRE) protocol permits multiple speculative waves of computation to be traversing a dataflow graph simultaneously, with a commit wave propagating behind them to ensure correct execution. We evaluate one application of this protocol to provide efficient recovery for load-store dependence speculation. Unlike traditional dataflow architectures which resorted to single-assignment memory semantics, the DSRE protocol combines dataflow execution with speculation to enable high performance and conventional sequential memory semantics. Our experiments show that the DSRE protocol results in an average 17% speedup over the best dependence predictor proposed to date, and obtains 82% of the performance possible with a perfect oracle directing the issue of loads.