Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order

  • Authors:

  • Jared Stark;Paul Racunas;Yale N. Patt

  • Affiliations:

  • Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan;Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan;Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan

  • Venue:
  • MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
  • Year:
  • 1997

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Abstract

In conventional processors, each instruction cache fetch brings in a group of instructions. Upon encountering an instruction cache miss, the processor will wait until the instruction cache miss is serviced before continuing to fetch any new instructions. This paper presents a new technique, called out-of-order issue, which allows the processor to temporarily ignore the instructions associated with the instruction cache miss. The processor attempts to fetch the instructions that follow the group of instructions associated with the miss. These instructions are then decoded and written into the processor's reservation stations. Later, after the instruction cache miss has been serviced, the instructions associated with the miss are decoded and written into the reservation stations. (We use the term issue to indicate the act of writing instructions into the reservation stations. With this technique, instructions are not written into the reservation stations in program order. Hence, the term out-of-order issue.) In this paper, we introduce the concept of out-of-order issue, describe its implementation, and present some initial data showing the performance gains possible with out-of-order issue.