Achieving high instruction cache performance with an optimizing compiler

  • Authors:

  • W. W. Hwu;P. P. Chang

  • Affiliations:

  • Coordinated Science Laboratory, University of Illinois, Urbana, IL;Coordinated Science Laboratory, University of Illinois, Urbana, IL

  • Venue:
  • ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
  • Year:
  • 1989

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Abstract

Increasing the execution power requires a high instruction issue bandwidth, and decreasing instruction encoding and applying some code improving techniques cause code expansion. Therefore, the instruction memory hierarchy performance has become an important factor of the system performance. An instruction placement algorithm has been implemented in the IMPACT-I (Illinois Microarchitecture Project using Advanced Compiler Technology - Stage I) C compiler to maximize the sequential and spatial localities, and to minimize mapping conflicts. This approach achieves low cache miss ratios and low memory traffic ratios for small, fast instruction caches with little hardware overhead. For ten realistic UNIX* programs, we report low miss ratios (average 0.5%) and low memory traffic ratios (average 8%) for a 2048-byte, direct-mapped instruction cache using 64-byte blocks. This result compares favorably with the fully associative cache results reported by other researchers. We also present the effect of cache size, block size, block sectoring, and partial loading on the cache performance. The code performance with instruction placement optimization is shown to be stable across architectures with different instruction encoding density.