Organization and VLSI implementation of MIPS
Advances in VLSI and Computer Systems
ATUM: a new technique for capturing address traces using microcode
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Lisp on a reduced-instruction-set processor: characterization and optimization
Lisp on a reduced-instruction-set processor: characterization and optimization
ACM Computing Surveys (CSUR)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
A study of branch prediction strategies
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Reduced Instruction Set Computer Architectures for VLSI
Reduced Instruction Set Computer Architectures for VLSI
Code optimization of pipeline constraints
Code optimization of pipeline constraints
Tags and type checking in LISP: hardware and software approaches
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A simulation study of two-level caches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A novel effective address calculation mechanism for RISC microprocessors
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
Efficient macro-code emulation in hardwired pipelined processors
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
A DCFL E/D-MESFET GaAs Experimental RISC Machine
IEEE Transactions on Computers
Achieving high instruction cache performance with an optimizing compiler
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Architectural and organizational tradeoffs in the design of the MultiTitan CPU
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Run-time checking in Lisp by integrating memory addressing and range checking
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
An architecture framework for application-specific and scalable architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
A flexible VLSI core for an adaptable architecture
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
IEEE Transactions on Computers
Reducing the branch penalty by rearranging instructions in a double-width memory
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
GT-EP: a novel high-performance real-time architecture
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming
IEEE Transactions on Computers
A RISC processor architecture with a versatile stack system
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
IEEE Transactions on Computers
Branch with masked squashing in superpipelined processors
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Branch classification: a new mechanism for improving branch predictor performance
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Minimizing branch misprediction penalties for superpipelined processors
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Control flow optimization for supercomputer scalar processing
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Instruction fetch unit for parallel execution of branch instructions
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Performance comparison of load/store and symmetric instruction set architectures
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Efficient Instruction Sequencing with Inline Target Insertion
IEEE Transactions on Computers
Code density concerns for new architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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The design of a RISC processor requires a careful analysis of the tradeoffs that can be made between hardware complexity and software. As new generations of processors are built to take advantage of more advanced technologies, new and different tradeoffs must be considered. We examine the design of a second generation VLSI RISC processor, MIPS-X.MIPS-X is the successor to the MIPS project at Stanford University and like MIPS, it is a single-chip 32-bit VLSI processor that uses a simplified instruction set, pipelining and a software code reorganizer. However, in the quest for higher performance, MIPS-X uses a deeper pipeline, a much simpler instruction set and achieves the goal of single cycle execution using a 2-phase, 20 MHz clock. This has necessitated the inclusion of an on-chip instruction cache and careful consideration of the control of the machine. Many tradeoffs were made during the design of MIPS-X and this paper examines several key areas. They are: the organization of the on-chip instruction cache, the coprocessor interface, branches and the resulting branch delay, and exception handling. For each issue we present the most promising alternatives considered for MIPS-X and the approach finally selected. Working parts have been received and this gives us a firm basis upon which to evaluate the success of our design.