Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
The g-machine: a fast, graph-reduction evaluator
Proc. of a conference on Functional programming languages and computer architecture
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The C programming language
Computer
Architectural tradeoffs in the design of MIPS-X
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The design and evaluation of a high performance Smalltalk system
The design and evaluation of a high performance Smalltalk system
MIPS RISC architecture
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
High-speed top-of-stack scheme for VLSI processor: a management algorithm and its analysis
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Efficient compilation of lazy evaluation
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
MC88100 Microprocessors User's Manual
MC88100 Microprocessors User's Manual
Performance measurement of a G-machine implementation
Proceedings of the Workshop on Graph Reduction
LFP '84 Proceedings of the 1984 ACM Symposium on LISP and functional programming
Compiling C on a Multiple-Stack Architecture
IEEE Micro
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Modern RISC processors mainly differ w.r.t, the organization of their register files. There are currently three different approaches: a flat register file (e.g., MIPS), fixed-size register windows (SPARC), or a stack-like organization (AM29K). This paper describes a processor architecture with a new stack system, which is tailored to the needs of executing functional languages. In order to support a fast subroutine call mechanism and efficient parameter passing, our architecture uses a system of four stacks, of which two are interchangeable.A simulation of this processor architecture shows that a selection of functional benchmark programs can be executed with less machine cycles than equivalent code-optimized C programs on a SPARC or MIPS processor.