Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
The design and evaluation of a high performance Smalltalk system
The design and evaluation of a high performance Smalltalk system
MIPS RISC architecture
A RISC processor architecture with a versatile stack system
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
The Implementation of Functional Programming Languages (Prentice-Hall International Series in Computer Science)
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A major distinguishing feature of RISC processor architectures is the organization of their register files. They basically fall into three categories: a flat register file as in MIPS processors, fixed--size register windows as in the SPARC processor line, and a stack-like organization as in the AM29K processors. The purpose of this paper is to introduce a RISC processor architecture Fast with a unique stack system. It has been designed with the special needs of functional languages in mind. To demonstrate the suitability of this architecture for conventional languages, we have implemented a C compiler for it. This paper gives an overview over the important parts of the architecture. It describes the adaptation of a standard C compiler to this architecture, and compares the resulting performance with SPARC and MIPS implementations.