Microprogrammable processor for object-oriented architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Coming to grips with a RISC: a report of the progress of the LOW RISC design group
ACM SIGARCH Computer Architecture News
Use of instruction set simulators to evaluate the LOW RISC
ACM SIGARCH Computer Architecture News
Branch folding in the CRISP microprocessor: reducing branch delay to zero
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
An evaluation of branch architectures
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
A plausibility-driven approach to computer architecture design
Communications of the ACM
A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
A priority strategy on RISC for real-time multitasking software applications
ACM SIGARCH Computer Architecture News
On reordering instruction streams for pipelined computers
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
On the mapping problem for multi-level systems
Proceedings of the 1989 ACM/IEEE conference on Supercomputing
Scheduling time-critical instructions on RISC machines
POPL '90 Proceedings of the 17th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The interaction of architecture and operating system design
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
GRIP: graphics reduced instruction processor
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Evaluation of A+B=K Conditions Without Carry Propagation
IEEE Transactions on Computers
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
A RISC processor architecture with a versatile stack system
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
Fast and accurate instruction fetch and branch prediction
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Formal Modeling and Verification of Microprocessors
IEEE Transactions on Computers
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
An instruction reoderer for pipelined computers
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Instruction fetch unit for parallel execution of branch instructions
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Highlight of VLSI at research Berkeley
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
Fast Prolog with an extended general purpose architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Scheduling time-constrained instructions on pipelined processors
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Comparison of RISC Architectures
IEEE Micro
Motorola's 88000 Family Architecture
IEEE Micro
Compiling C on a Multiple-Stack Architecture
IEEE Micro
Reducing Branch Delay to Zero in Pipelined Processors
IEEE Transactions on Computers
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Fred: An Architecture for a Self-Timed Decoupled Computer
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A stack addressing scheme based on windowing
ACM SIGARCH Computer Architecture News
A multiple application graphics integrated circuit MAGIC II
EGGH'87 Proceedings of the Second Eurographics conference on Advances in Computer Graphics Hardware
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