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SIAM Journal on Computing
Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
Incremental foresighted local compaction
MICRO 22 Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Scheduling real-time computations with separation constraints
Information Processing Letters
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Foresighted Instruction Scheduling Under Timing Constraints
IEEE Transactions on Computers
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Iterative modulo scheduling: an algorithm for software pipelining loops
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Region-based compilation: an introduction and motivation
Proceedings of the 28th annual international symposium on Microarchitecture
Single machine scheduling subject to precedence delays
Discrete Applied Mathematics
Microcode compaction with timing constraints
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Building a retargetable local instruction scheduler
Software—Practice & Experience
Efficiency of a Good But Not Linear Set Union Algorithm
Journal of the ACM (JACM)
Scheduling Tasks with Nonuniform Deadlines on Two Processors
Journal of the ACM (JACM)
Complexity results for single-machine problems with positive finish-start time-lags
Computing - Special issue on combinatorial optimization
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
A linear-time algorithm for a special case of disjoint set union
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
On the Complexity of Precedence Constrained Scheduling
On the Complexity of Precedence Constrained Scheduling
Embedded Systems: Challenges in Specification and Verification
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Data-Dependency Graph Transformations for Instruction Scheduling
Journal of Scheduling
Data-Dependency Graph Transformations for Superblock Scheduling
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
The arrow of time through the lens of computing
Time for verification
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In this work we investigate the problem of scheduling instructions on idealized microprocessors with multiple pipelines, in the presence of precedence constraints, release-times, deadlines, and latency constraints. A latency of lij specifies that there must be at least lij time-steps between the completion time of instruction i and the start time of instruction j. A latency of lij=−1 can be used to specify that j may be scheduled concurrently with i but not earlier. We present a generic algorithm that runs in O(n2logn&agr;(n)+ne) time, givenn instructions and e edges in the precedence DAG, where &agr;(n) is the functional inverse of the Ackermann function. Our algorithm can be used to construct feasible schedules for various classes of instances, including instances with the following configurations: (1) one pipeline, with individual release-times and deadlines and where the latencies between instructions are restricted to 0 and 1; (2) m pipelines, with individual release-times and deadlines, and monotone-interval order precedences; (3) two pipelines with latencies of −1 or 0, and release-times and deadlines; (4) one pipeline, latencies of 0 or 1 and individual processing times that are at least one; (5) m pipelines, intree precedences, constant latencies, and deadlines; (6) m pipelines, outtree precedences, constant latencies, and release-times. For instances with deadlines, optimal schedules that minimize the maximal tardiness can be constructed using binary search, in O(log n) iterations of our algorithm. We obtain our results using backward scheduling, a very general relaxation method, which extends, unifies, and clarifies many previous results on instruction scheduling for pipelined and parallel machines.