On some variants of the bandwidth minimization problem
SIAM Journal on Computing
Reduced instruction set computer architectures for VLSI
Reduced instruction set computer architectures for VLSI
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Scheduling expressions on a pipelined processor with a maximal delay of one cycle
ACM Transactions on Programming Languages and Systems (TOPLAS)
Scheduling Uet systems on two uniform processors and length two pipelines
SIAM Journal on Computing
Loop quantization of unwinding done right
Proceedings of the 1st International Conference on Supercomputing
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Approximation algorithms for scheduling arithmetic expressions on pipelined machines
Journal of Algorithms
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Efficiency of a Good But Not Linear Set Union Algorithm
Journal of the ACM (JACM)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code generation and reorganization in the presence of pipeline constraints
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Loop Quantization: an Analysis and Algorithm
Loop Quantization: an Analysis and Algorithm
On the Complexity of Precedence Constrained Scheduling
On the Complexity of Precedence Constrained Scheduling
Allocating registers in multiple instruction-issuing processors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Anticipatory instruction scheduling
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Concurrent Detection of Software and Hardware Data-Access Faults
IEEE Transactions on Computers
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Scheduling time-constrained instructions on pipelined processors
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Dynamic Programming Approach to Optimal Integrated Code Generation
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies
CP '02 Proceedings of the 6th International Conference on Principles and Practice of Constraint Programming
Fast Optimal Instruction Scheduling for Single-Issue Processors with Arbitrary Latencies
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
Variable Instruction Set Architecture and Its Compiler Support
IEEE Transactions on Computers
Compiler optimization of embedded applications for an adaptive SoC architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
WCET-aware data selection and allocation for scratchpad memory
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
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We present a polynomial time algorithm for constructing a minimum completion time schedule of instructions from a basic block on RISC machines such as the Sun SPARC, the IBM 801, the Berkeley RISC machine, and the HP Precision Architecture. Our algorithm can be used as a heuristic for RISC processors with longer pipelines, for which there is no known optimal algorithm. Our algorithm can also handle time-critical instructions, which are instructions that have to be completed by a specific time. Time-critical instructions occur in some real-time computations, and can also be used to make shared resources such as registers quickly available for reuse. We also prove that in the absence of time-critical constraints, a greedy scheduling algorithm always produces a schedule for a target machine with multiple identical pipelines that has a length less than twice that of an optimal schedule. The behavior of the heuristic is of interest because, as we show, the instruction scheduling problem becomes NP-hard for arbitrary length pipelines, even when the basic block of code being input consists of only several independent streams of straightline code, and there are no time-critical constraints. Finally, we prove that the problem becomes NP-hard even for small pipelines, no time-critical constraints, and input of several independent streams of straightline code if either there is only a single register or if no two instructions are allowed to complete simultaneously because of some shared resource such as a bus.