Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
MIPS RISC architecture
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums
IEEE Transactions on Computers
An empirical study of the reliability of UNIX utilities
Communications of the ACM
The C programming language
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Alpha architecture reference manual
Alpha architecture reference manual
New CPU benchmark suites from SPEC
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
Scheduling time-critical instructions on RISC machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
FINE: A Fault Injection and Monitoring Environment for Tracing the UNIX System Behavior Under Faults
IEEE Transactions on Software Engineering - Special issue on software reliability
Efficient detection of all pointer and array access errors
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
A brief survey of papers on scheduling for pipelined processors
ACM SIGPLAN Notices
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring
IEEE Transactions on Computers
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Performance Evaluation of Exception Handling in I/O Libraries
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Robustness Testing and Hardening of CORBA ORB Implementations
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring
IEEE Transactions on Computers
Micro embedded monitoring for security in application specific instruction-set processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Hi-index | 14.98 |
A new approach allows low-cost concurrent detection of two important types of faults, software and hardware data-access faults, using an extension of the existing signature monitoring approach. The proposed approach detects data-access faults using a new type of redundant data structure that contains an embedded signature. Low-cost fault detection is achieved using simple architecture support and compiler support that exploit natural redundancies in the data structures, in the instruction set architecture, and in the data-access mechanism. The software data-access faults that the approach can detect include faults that have been shown to cause a high percentage of system failures. Hardware data-access faults that occur in all levels of the data-memory hierarchy are also detectable, including faults in the register file, the data cache, the data-cache TLB, the memory address and data buses, etc. Benchmark results for the MIPS R3000 processor executing code scheduled by a modified GNU C Compiler show that the new approach can concurrently check a high percentage of data accesses, while causing little performance overhead and little memory overhead.