Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
A roving monitoring processor for detection of control flow errors in multiple processor systems
Microprocessing and Microprogramming - Fault tolerant computing
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Comparative analysis of computer architectures
Comparative analysis of computer architectures
Concurrent Detection of Software and Hardware Data-Access Faults
IEEE Transactions on Computers
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring
IEEE Transactions on Computers
Concurrent Process Monitoring with No Reference Signatures
IEEE Transactions on Computers
Linear Complexity Assertions for Sorting
IEEE Transactions on Software Engineering
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Software-Based Transparent and Comprehensive Control-Flow Error Detection
Proceedings of the International Symposium on Code Generation and Optimization
Dynamic binary control-flow errors detection
ACM SIGARCH Computer Architecture News - Special issue on the 2005 workshop on binary instrumentation and application
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-line control flow error detection using relationship signatures among basic blocks
Computers and Electrical Engineering
An optimal number of microprocessor units with watchdog processor
Mathematical and Computer Modelling: An International Journal
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A control-flow checking method using extended-precision checksums and watchdog assists is proposed. Control-flow checking based on extended-precision checksums is shown to have low error detection latency compared to previously proposed methods. Analytical measures are derived to demonstrate the effectiveness of using extended-precision checksums for control flow checking. It is shown that the error detection latency in the extended-precision-checksum-based control-flow checking remains relatively constant for both single and multiple sequence errors. In the case of signature-based methods, error detection latency increases linearly with the number of sequence errors. A watchdog assist architecture for control-flow checking in programs which addresses several architecture issues is proposed. This watchdog assist architecture can support control-flow checking for multiprocessor, multiprogramming, and cache-based environments. The Hewlett-Packard Precision Architecture is used as an example architecture to demonstrate the feasibility of watchdog assists.