Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Design of systems with concurrent error detection using software redundancy
Design of systems with concurrent error detection using software redundancy
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums
IEEE Transactions on Computers
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Software Fault Tolerance
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Evaluation of integrated system-level checks for on-line error detection
IPDS '96 Proceedings of the 2nd International Computer Performance and Dependability Symposium (IPDS '96)
System safety through automatic high-level code transformations: an experimental evaluation
Proceedings of the conference on Design, automation and test in Europe
On-line fault detection in a hardware/software co-design environment: system partitioning
Proceedings of the 14th international symposium on Systems synthesis
Reliability Properties Assessment at System Level: A Co-Design Framework
Journal of Electronic Testing: Theory and Applications
Experimental Evaluation of Fault Handling Mechanisms
SAFECOMP '01 Proceedings of the 20th International Conference on Computer Safety, Reliability and Security
A Framework for Database Audit and Control Flow Checking for a Wireless Telephone Network Controller
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
An Experimental Study of Security Vulnerabilities Caused by Errors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Journal of Electronic Testing: Theory and Applications
Reliable System Specification for Self-Checking Data-Paths
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring
IEEE Transactions on Computers
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
IEEE Transactions on Computers
Software-Based Transparent and Comprehensive Control-Flow Error Detection
Proceedings of the International Symposium on Code Generation and Optimization
Dynamic binary control-flow errors detection
ACM SIGARCH Computer Architecture News - Special issue on the 2005 workshop on binary instrumentation and application
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
An optimized hybrid approach to provide fault detection and correction in SoCs
Proceedings of the 20th annual conference on Integrated circuits and systems design
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Journal of Electronic Testing: Theory and Applications
Software and Hardware Techniques for SEU Detection in IP Processors
Journal of Electronic Testing: Theory and Applications
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
Journal of Electronic Testing: Theory and Applications
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
On-line control flow error detection using relationship signatures among basic blocks
Computers and Electrical Engineering
FlowChecker: Detecting Bugs in MPI Libraries via Message Flow Checking
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
A hybrid hardware--software technique to improve reliability in embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 24th symposium on Integrated circuits and systems design
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage
Journal of Electronic Testing: Theory and Applications
Time-Constraint-Aware Optimization of Assertions in Embedded Software
Journal of Electronic Testing: Theory and Applications
Low cost control flow protection using abstract control signatures
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
A survey of checker architectures
ACM Computing Surveys (CSUR)
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This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect control flow errors. We propose Enhanced Control-Flow Checking Using Assertions (ECCA). In ECCA, branch-free intervals (BFI) in a given high or intermediate level program are identified and the entry and exit points of the intervals are determined. BFIs are then grouped into blocks, the size of which is determined through a performance/overhead analysis. The blocks are then fortified with preinserted assertions. For the high level ECCA, we describe an implementation of ECCA through a preprocessor that will automatically insert the necessary assertions into the program. Then, we describe the intermediate implementation possible through modifications made on gcc to make it ECCA capable. The fault detection capabilities of the checks are evaluated both analytically and experimentally. Fault injection experiments are conducted using FERRARI [1] to determine the fault coverage of the proposed techniques.