Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums
IEEE Transactions on Computers
Custom-fit processors: letting applications define architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
Customized instruction-sets for embedded processors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Software Fault Tolerance
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Concurrent Process Monitoring with No Reference Signatures
IEEE Transactions on Computers
Hierarchical Error Detection in a Software Implemented Fault Tolerance (SIFT) Environment
IEEE Transactions on Knowledge and Data Engineering
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Evaluation of integrated system-level checks for on-line error detection
IPDS '96 Proceedings of the 2nd International Computer Performance and Dependability Symposium (IPDS '96)
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Soft-Error Detection Using Control Flow Assertions
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Rapid Embedded Hardware/Software System Generation
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Processor Description Languages
Processor Description Languages
Evaluation and analysis of an on-line error detection monitoring technique
Computers and Electrical Engineering
Leveraging speculative architectures for runtime program validation
ACM Transactions on Embedded Computing Systems (TECS)
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Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardware-assisted approaches are not scalable and therefore cannot be implemented in real embedded systems. This paper presents a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications. While architectural refinement incorporates additional instructions, the software transformation utilizes these instructions into the program flow. Applications from an embedded systems benchmark suite are used for testing and evaluation. The overheads are compared with the state of the art approach that performs the same error coverage using software-only techniques. Our method has greatly reduced overheads compared to the state of the art. Our approach increased code size by between 3.85-11.2% and reduced performance by just 0.24-1.47% for eight different industry standard applications. The additional hardware (gates) overhead in this approach was just 3.59%. In contrast, the state of the art software-only approach required 50-150% additional code, and reduced performance by 53.5-99.5% when error detection was inserted.