Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
On-line fault detection in a hardware/software co-design environment: system partitioning
Proceedings of the 14th international symposium on Systems synthesis
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Journal of Electronic Testing: Theory and Applications
Reliable System Specification for Self-Checking Data-Paths
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
Journal of Electronic Testing: Theory and Applications
A hybrid hardware--software technique to improve reliability in embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Agent-based error prevention algorithms
Expert Systems with Applications: An International Journal
A survey of checker architectures
ACM Computing Surveys (CSUR)
| Hi-index | 0.00 |
This paper evaluates the capabilities of an integrated system level error detection technique using fault and error injection. This technique is comprised of two software level mechanisms for concurrent error detection, control flow checking using assertions (CCA) and data error checking using application specific data checks. Over 300,000 faults and errors were injected and the analysis of the results reveals that the CCA detects 95% of all the errors while the data checks are able to detect subtle errors that go undetected by the CCA technique. Latency measurements also shelved that the CCA technique is faster than the data checks in detecting the error. When both techniques were incorporated, the system was able to detect over 98% of all injected errors.