Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features

Authors:
Amir Rajabzadeh;Seyed Ghassem Miremadi;Mirzad Mohandespour
Affiliations:
Dependable Systems Laboratory (DSL), Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran. rajabzad@ce.sharif.edu;Dependable Systems Laboratory (DSL), Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran. miremadi@sharif.edu;Dependable Systems Laboratory (DSL), Department of Computer Engineering, Sharif University of Technology, Azadi Ave., Tehran, Iran. mohandes@ce.sharif.edu
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

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Abstract

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This paper presents an error detection scheme called Committed Instructions Counting (CIC) to increase error detection in such systems. The scheme uses internal Performance Monitoring features and an external watchdog processor (WDP). The Performance Monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium® processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium® processor. The results show that the error detection coverage varies between 90.92 and 98.41%, for different workloads. To verify the experimental results an analytical evaluation of the coverage is also performed.