Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
IEEE Transactions on Parallel and Distributed Systems
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
Journal of Electronic Testing: Theory and Applications
Using loop invariants to fight soft errors in data caches
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improving scratch-pad memory reliability through compiler-guided data block duplication
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
Software-Based Failure Detection and Recovery in Programmable Network Interfaces
IEEE Transactions on Parallel and Distributed Systems
Applying Safety Goals to a New Intensive Care Workstation System
SAFECOMP '08 Proceedings of the 27th international conference on Computer Safety, Reliability, and Security
AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware
SAFECOMP '09 Proceedings of the 28th International Conference on Computer Safety, Reliability, and Security
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage
Journal of Electronic Testing: Theory and Applications
Memory space conscious loop iteration duplication for reliable execution
SAS'05 Proceedings of the 12th international conference on Static Analysis
Software encoded processing: building dependable systems with commodity hardware
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
Evaluation and analysis of an on-line error detection monitoring technique
Computers and Electrical Engineering
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In this paper is described a software technique allowing to detect soft errors occurring in processor-based digital architectures. The detection mechanism is based on a set of rules allowing the transformation of the target application into a new one, having same functionalities but being able to identify bit-flips arising in memory areas as well as those perturbing the processorýs internal registers. Experimental results issued from fault injection sessions and preliminary radiation test campaigns performed in complex DSP processor, provide objective figures about the efficiency of the proposed error detection technique.