Modulo 3 Residue Checker: New Results on Performance and Cost
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Modular Error Detection for Bit-Serial Multiplication
IEEE Transactions on Computers
On Subsequences of Arithmetic Sequences
IEEE Transactions on Computers
From defects to failures: a view of dependable computing
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
A New Residue Arithmetic Error Correction Scheme
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
New Encoding/Decoding Methods for Designing Fault-Tolerant Matrix Operations
IEEE Transactions on Parallel and Distributed Systems
A high-level synthesis approach to optimum design of self-checking circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A FPGA-based implementation of a fault-tolerant neural architecture for photon identification
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
High Performance Fault-Tolerant Digital Neural Networks
IEEE Transactions on Computers
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
High-Speed Parallel-Prefix Modulo 2n - 1 Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
Journal of VLSI Signal Processing Systems
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Asymmetric binary covering codes
Journal of Combinatorial Theory Series A
Majority-Logic-Decodable Cyclic Arithmetic-Modular AN-Codes in 1, 2, and L Steps
Proceedings of the 8th IMA International Conference on Cryptography and Coding
Bit-modular defect/fault-tolerant convolvers
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
Error Analysis for the Support of Robust Voltage Scaling
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Error-Correcting Codes for Byte-Organized Arithmetic Processors
IEEE Transactions on Computers
Error-Correcting Codes in Binary-Coded Radix-r Arithmetic
IEEE Transactions on Computers
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
An Algebraic Model of Arithmetic Codes
IEEE Transactions on Computers
Near-Perfect Codes for Binary-Coded Radix-r Arithmetic Units
IEEE Transactions on Computers
Theory of Unidirectional Error Correcting/Detecting Codes
IEEE Transactions on Computers
Single Asymmetric Error-Correcting Cyclic AN Codes
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
A Direct Method of Computing the GNAF of an Integer
IEEE Transactions on Computers
Some Results on the Arithmetic Correlation of Sequences
SETA '08 Proceedings of the 5th international conference on Sequences and Their Applications
Fault-tolerant modularized arithmetic logic units
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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