VLSI array processors
Digital image processing
Two-Dimensional Digital Signal Processing II: Transforms and Median Filters
Two-Dimensional Digital Signal Processing II: Transforms and Median Filters
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
A bit-level systolic array for median filter
IEEE Transactions on Signal Processing
On VLSI design of rank-order filtering using DCRAM architecture
Integration, the VLSI Journal
ADVIS'04 Proceedings of the Third international conference on Advances in Information Systems
Efficient distortion reduction of mixed noise filters by neuro-fuzzy processing
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part II
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Several DSP algorithms need to remove high-frequency or impulsive noise while preserving edges, e.g., in speech and image processing applications: median filtering has been proved to be more effective for achieving this goal than other filtering techniques. Efficient architectural implementation for real-time applications involves a careful VLSI design, which takes into account modularity, regularity, adaptability, scalability, throughput, circuit complexity and fault tolerance.Four new architectural approaches are presented and evaluated in this paper to deal with different application and implementation constraints. They are: the serial-input polarizing median filter, the floating median filter, the pipelined polarizing median filter and the pipelined sorting median filter. The 1st and the 2nd architectures are based on majority voting, while the 3rd and the 4th ones are based on sorting techniques. All of them are designed so as to exhibit high scalability and to be easily pipelined for higher working frequencies.