Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Efficient adaptive voltage scaling system through on-chip critical path emulation
Proceedings of the 2004 international symposium on Low power electronics and design
Secure multipliers resilient to strong fault-injection attacks using multilinear arithmetic codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the minimum supply voltage even if occasional errors result. To determine which technique can reliably and efficiently detect such failures, it is necessary to understand the manner in which digital designs fail at critical voltages. In this paper, we report hardware measurements of the failure modes of a multiplier circuit under voltage scaling. We show that even at small error rates, it is necessary to deal with multiple errors where bits are flipped from both 0 to 1 and 1 to 0. Intra- and inter-die variations make the exact nature of these flips unpredictable. This suggests that conventional single and unidirectional error detectors will not work. We conclude that the most suitable solution is a simple delay-error tolerant flip-flop that detects and corrects errors by double sampling signals.